1. Field of the Invention
This invention relates to FIFO (First-in/First-out) memories and more particularly relates to an improved FIFO serial shift-register memory which operates with decreased fall-through delay.
2. Description of Related Art
FIFO memories are widely used as intermediate buffers where there is a need to transfer binary data between systems or devices which operate at different frequencies and where the order of the data must remain unchanged. These devices are often constructed of multiple shift-register stages coupled for cascade operation. Data is clocked into the first shift register stage at some shift-in frequency, and after a certain latency time or fall-through delay, the data is clocked out of the last stage at a different shift-out frequency. The fall-through delay is the time it takes from data to propagate through the FIFO, from input to output.
It is desirable for a FIFO to have large storage capacity, or length, sufficient to hold an entire block of data from a slower data-handling device to a much faster one. However, where the capacity of the FIFO is large, typically 256 bytes, the fall-through delay becomes long, particularly when the FIFO is empty and new data is entered into it, negatively affecting performance and placing unwanted constraints on system design.
In the prior art, efforts to deal with the problems of FIFOs have been varied but only marginally effective. One approach has been to design FIFO buffers using random access memories. A device of this type is the MK4501 FIFO manufactured by Mostek, Inc. of Carrollton, Tex. In general, RAM-type FIFOs can buffer large blocks of data and recall the data quickly. However, in order to read from and write to the FIFO simultaneously, the RAM must be dual-ported or have sufficient control logic to simulate dual port operation. In addition, complex circuitry must be employed to keep track of the data locations in the RAM. The additional counter and control circuitry increases the complexity of the device and slows down the rate at which data can be accessed.
U.S. Pat. No. 4,314,361 to Jansen et al. discloses another FIFO memory device of the shift register type, having a single, fixed input and a variable output. In this patent, each memory stage is connected to an output bus and logic circuitry selects the stage from which data is extracted from the buffer. This device has reduced fall-through delay, since data need not travel through the entire FIFO; however, to buffer large blocks of data, it cannot easily be constructed in integrated circuit form, which would be highly desirable. Each memory stage requires independent transistors for driving an output bus, and the involved wiring, complexity, increased chip area, and the high-power dissipation problems would render such a device impractical. There is a need for a FIFO which is designed so as to minimize the fall-through delay, yet be simple and cost effective, while also lending itself to manufacture as an integrated circuit.